1. Field of the Invention
The present invention relates to line drivers, and more particularly to high-speed, low-distortion line drivers.
2. Related Art
FIG. 1 shows a conventional output driver cell of a line driver currently employed in (Gigabit) Ethernet products. Each cell includes two differential pairs, enabling tri-state operation. Transistors M1a through M1d are cascodes, implemented using thick-oxide transistors. Transistors M3a and M3b implement the tail current sources of the two differential pairs, each providing a current IBIAS. Transistors M2a through M2d are switches (typically thin-oxide transistors) that control to which output terminal the bias current IBIAS is sent. More specifically, when Vswitch1 and Vswitch3 are logical xe2x80x9c1xe2x80x9d, and Vswitch2 and Vswitch4 are xe2x80x9c0xe2x80x9d, the differential output current IOUT equals xe2x88x922IBIAS. When Vswitch1 and Vswitch3 are xe2x80x9c0xe2x80x9d, and Vswitch2 and Vswitch4 are xe2x80x9c1xe2x80x9d, IOUT equals 2 IBIAS. When Vswitch1 through Vswitch4 are all xe2x80x9c1xe2x80x9d, IOUT equals zero. (In other words, the digital signal, or data signal, activates the switching transistors M2a-M2d.) A more detailed description of a conventional line driver can be found in commonly assigned U.S. Pat. No. 6,259,745.
VBIAS is a DC bias voltage that biases the tail current transistors M3a, M3b to an analog amplifier mode. The switches M2a-M2d send current to either the xe2x80x9c+xe2x80x9d or the xe2x80x9cxe2x88x92xe2x80x9d terminal of the output cell, which is a tri-state operating cell. The cell outputs either 2IBIAS, 0, or xe2x88x922IBIAS. To output zero current, while operating the cell in class B mode, gates of switches M2a-M2d are switched to ground, and no current appears at the output. Due to the charge injected at node {circle around (1)}, the potential at the gate of M3 changes, resulting in distortion. Thus, there is unwanted modulation of the DC bias on the gate of the tail current transistors M3a, M3b. 
As noted above, when IOUT has to be zero, Vswitch1 through Vswitch4 switch to xe2x80x9c0xe2x80x9d. Unfortunately, switching off all four switches M2a-M2d results in significant distortion of the output signal IOUT. The cause of the distortion is explained by FIG. 2, which shows half of a line driver output cell. The distortion occurs when all four switches M2a-M2d are switched to xe2x80x9c0xe2x80x9d. In that case, node {circle around (2)} goes to ground potential. Through the parasitic capacitance Cp, charge is injected onto node {circle around (1)}. In general, the bias voltage VBIAS is generated by a current-biased diode, which has a finite output impedance modeled by RBIAS. Furthermore, the parasitic capacitance Cp,bias associated with the bias voltage VBIAS source and transistor M3 is quite large. As a consequence, the charge injected onto node {circle around (1)} causes the voltage on node {circle around (1)} to drop. It settles back slowly due to the finite voltage source impedance and the large parasitic capacitance connected to node {circle around (1)}. This results in modulation of the tail currents of the differential pairs, and therefore, in modulation of the amplitude of IOUT, in other words, unwanted distortion.
IOUT (in differential mode)=IOUT+xe2x88x92IOUTxe2x88x92. IOUT is the differential output signal current. Its magnitude depends on the symbol to be transmitted and varies from xe2x88x9240 mA to 40 mA (in 1000BT, 100TX mode), from xe2x88x92100 mA to 100 mA(in 10BT mode). In Class AB mode, ICOMMONxe2x80x94MODE=(IOUT+xe2x88x92IOUTxe2x88x92)/2 varies from 20 mA to 10 mA, depending on the symbol to be transmitted. Thus:
ICOMMONxe2x80x94MODE=20 mA (in Class-A mode).
ICOMMONxe2x80x94MODE varies from 20 mA to 10 mA (in Class-AB mode), hence the maximum saving of current is 10 mA. When ICOMMONxe2x80x94MODE switches from 20 mA to 10 mA, a glitch is seen that eventually settles to constant valuexe2x80x94i.e., producing unwanted distortion.
The present invention is directed to a line driver that substantially obviates one or more of the problems and disadvantages of the related art.
There is provided a differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding the first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.
In another aspect of the present invention there is provided a differential line driver including first and second half-cells, the half-cells cross connected to positive and negative differential outputs, each half-cell including first and second cascode transistors connected in parallel. First and second switching transistors are connected in series with the first and second cascode transistors and driven by a data signal. A first compound transistor inputs a class AB operation signal at its gate and connected to sources of the first and second switching transistors.
In another aspect of the present invention there is provided a differential line driver includes first and second half-cells, the half-cells cross connected to positive and negative differential outputs, each half-cell including first and second cascode transistors are connected in parallel. First and second switching transistors are connected in series with the first and second cascode transistors and driven by a voltage. A tail current transistor inputs a bias voltage at its gate and connected to sources of the first and second switching transistors, wherein a sum of charge injection at the gate of the tail current transistor is substantially zero during switching.
In another aspect of the present invention there is provided a class AB line driver including first and second half-cells cross connected to positive and negative differential outputs, each half-cell including first and second cascode transistors connected in parallel. First and second switching transistors are connected in series with the first and second cascode transistors. A tail current transistor inputs a bias voltage at its gate and connected to sources of the first and second switching transistors, wherein the bias voltage spikes last less than a clock cycle during switching for Gigabit Ethernet operation.
In another aspect of the present invention there is provided a programmable line driver including a plurality of cells, each cell selectively controlled by class AB operation signal and each cell including first and second half-cells cross connected to outputs of opposite polarity, each half-cell including first and second parallel cascode transistors. First and second switching transistors are each connected in series with the first and second parallel cascode transistors. A compound transistor inputs a bias signal at its gate and connected to sources of the first and second switching transistors, the compound transistor switched to class AB operation by the class AB operation signal, wherein same polarity outputs of the cells are added.
In another aspect of the present invention there is provided a differential line driver including a plurality of cascode transistors connected in parallel and to corresponding polarity outputs of the differential line driver. A plurality of switching transistors are connected in series with corresponding cascode transistors. A plurality of compound transistors input a class AB operation signal at their gates and connected in series with corresponding switching transistors.
In another aspect of the present invention there is provided a differential line driver including first and second half-cells, the half-cells cross connected to positive and negative differential outputs, each half-cell including first and second cascode transistors connected in parallel. First and second switching transistors connected in series with the first and second cascode transistors. A variable effective channel length transistor inputting a signal that changes its effective channel length at its gate and connected to sources of the first and second switching transistors.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.